Semiconductor and Systems companies have embraced the fabless model, making IP Reuse a critical design directive for achieving higher returns on assets, cost cutting, time to market and enhanced profitability. While there are a variety of approaches to making an IP inherently reuseable it has become apparent to those of us at IC Manage that the collaboration between IP creator and SOC integrator is less than optimal. Our focus on optimizing the collaboration is the inspiration for our reuse platform, IP Central.
Whether soft or hard, IP design involves the usual process of repeatedly finding and fixing bugs. Many bugs aren't found until the IP is simulated along with it surrounding blocks. And of course, in some cases an IP is just the starting point for a derivative IP. Multiple SOC integration managers are looking at an IP at different times, often after the original IP designer has moved on. No longer can the SOC developer simply copy a directory and blaze their own trail. The point is that IP is a dyanamic IP living asset - not just a netlist put on the shelf for others to grab.
SOC integrators are the real IP customers and they want to know every detailed characteristic about every IP available to them within their company, including its detailed development status, silicon worthiness and geneology so they can make informed decisions about usage. IP Cental is a powerful reuse platform which centralizes access to IP across the company regardless of the server it is stored on. Bug dependencies are tracked across entire development trees. It also includes powerful and customizable analytics that allow managers to visualize how the IP is being utilized within the company.
Interested in learning more? Download the IP Central datasheet.
Read the technical white paper "Best Practices for Maximizing IP Reuse in SoC, IC and FPGA Design".
Watch the IP Central demonstration.