GDP Design Data Management for Cadence Virtuoso

Using IC Manage GDP for Collaborative Custom IC (Virtuoso) and Digital SOC Design

It is critical to tighten and streamline the information flow between design layers and team members to produce a functional SOC on time and at budget. Tools that assist the design process and team collaboration are as vital to completing the SOC as the individual tools used to build the design. 

SOC design contains the familiar levels of the silicon design and implementation (behavioral through layout) as well as a software layer (including firmware, device drivers...). Each layer represents a world view of the SOC at a different level of abstraction and utilizes a different set of tools to realize its function. The subsystems are typically implemented with internally and externally generated IP.

Moving between these domains can be difficult. Design goals such as power, area, and performance can span multiple layers. Additionally, verification must be addressed across all levels of the design stack. The SOC must be developed and applied against a churning of project changes. The design flow must be sufficiently robust to deal with changes occurring simultaneously on all levels as work progresses. 

This white paper explores the typical components, processes and flows used to create an SOC, as well as the intricacies of collaboration among interdependent design teams. It will also show how IC Manage's Global Design Platform (GDP) can serve as a foundation for unifying the entire SOC design and verification process, and illustrates how it works for Custom IC Design with Cadence Virtuoso. GDP uses shared workspaces and change-based design methods that efficiently deal with constant changes and propagating those changes as needed for both the initial design and all the derivatives. 

This whitepaper covers:

1.    The SOC Design Layers

2.    Global, Interdependent Teams

3.    Globalizing the Collaborative Environment through Workspaces

- Design Partitioning by Data Type

- Partitioning Design Space by Design Unit

4. Change-Driven SOC Design

5. Using GDP for Custom IC Design: Cadence Virtuoso Illustration

6. Managing Digital Designs with GDP

7. Managing Verification Changes with GDP: JIRA Illustration

8. Monitoring Project Progress

9. Handling Design Releases

10. Managing IP and Derivative Designs

11. Managing Third Party IP


To download the whitepaper click here.